Master Thesis #1 – Optimization of the Video/AI Pipeline and GPU Acceleration on Nvidia Jetson Platform Title : « Optimization of the Video/AI Pipeline and GPU Acceleration on Nvidia Jetson Platform » Target audience : Computer Science / Bachelor, Master, Computer or Electronics Engineering Type : Supervisors : Christophe Seyler / Jean-Christophe Lallemand Internal competence center : Embedded / PC System […]
Hardware Intership #1 Title : FPGA Development Intern – IP10 CoDec Implementation Target : Electronics engineer In-house competence centers : FPGA / Video / Compression Job description : We are looking for a motivated and technically skilled intern to join our development team. The intern will work closely with our engineers to design and implement an IP10 CoDec (coder-decoder)
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